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nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 1 256mb m-die mlc nor specification information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure couldresult in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * samsung electronics reserves the right to change products or specification without notice.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 2 document title 256m bit (16m x16) muxed burst , multi bank mlc nor flash memory revision history revision no. 0.0 0.1 0.2 0.3 0.4 0.5 remark preliminary preliminary preliminary preliminary preliminary preliminary history initial revision tcez is changed. 20ns==>15ns 44fbga pkg diagram is added package diagram is added (new format) dpd pin assignment is changed d6 ==> c7 ac parameters are changed tba : 8ns ==> 9ns (@83mhz) tbdh : 1.5ns ==> 3ns (@66mhz, 83mhz), 2ns (@133mhz) toe : 20ns ==> 15ns trdya : 8ns ==> 9ns (@83mhz) trdys : 4ns (@66mhz, 83mhz), 1.5ns (@133mhz) ==> 3ns (@66mhz, 83mhz), 2ns (@133mhz) toer : 20ns ==> 11ns (@66mhz), 9ns (@83mhz), 6ns (@133mhz) active write current 15ma (typ.), 30ma (max.) ==> 25ma (typ.), 40ma (max.) correct typo add speed characteristic for 108mhz sync burst read add ordering information for density ==> 56 : 256mb for 66/83mhz ==> 57 : 267mb for 108/133mhz add product classification table (table 1-1) change tavdh(avd hold time from clk) 6ns(@66mhz) ==> 2ns(@66mhz) 5ns(@83mhz) ==> 2ns(@83mhz) change taavdh(address hold time from rising edge of avd ) 7ns(@66mhz) ==> 2ns(@66mhz) 5ns(@83mhz) ==> 2ns(@83mhz) change tces(ce setup time to clk) 4.5ns(@83/133mhz) ==> 6ns(@83/133mhz) change toez(output disable to high z 10ns(@66/83mhz) ==> 15ns(@66/83mhz) add description and figure of dpd correct typo move address tables to the end of specification correct note number on command sequence table change t ghwl (read recovery time before write) 0ns(typ.) ==> 0ns(min.) change t wp (we pulse width) 60ns(typ.) ==> 60ns(min.) change t wph (we pulse width high) 40ns(typ.) ==> 40ns(min.) draft date october 17, 2005 october 19, 2005 october 26,2005 november 10,2005 december 20,2005 january 05,2006
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 3 revision no. 0.6 1.0 1.1 1.2 remark preliminary history cfi note is added (max operation frequency : data 53h is in 66/ 83mhz part toez value is changed min 15ns to max 15ns specification is finalized active asynchronous read current(@1mhz) is changed 3ma(typ.),5ma(max.) to 8ma(typ.), 10ma(max.) ?in erase/program suspend followed by resume operation, min. 200ns is needed for checking the busy status? is added frequency information is added to programmable wait state at burst mode configuration register table. " asynchronous mode may not support read following four sequential invalid read condition within 200ns." is added correct typo draft date april 04, 2006 april 20,2006 september 08, 2006 september 28, 2006
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 4 256m bit (16m x16) muxed burst , multi bank mlc nor flash memory the k8f56(57)15e featuring single 1.8v power supply is a 256mbit muxed burst multi bank flash memory organized as 16mx16. the memory architecture of the device is designed to divide its memory arrays into 259 blocks with independent hard- ware protection. this block archit ecture provides highly flexible erase and program capability. the k8f56(57)15e nor flash consists of sixteen banks. this device is capable of reading data from one bank while programming or erasing in the other bank. regarding read access time, the k8f5615e provides an 11ns burst access time and an 100ns initial access time at 66mhz. at 83mhz, the k8f5615e provides an 9ns burst access time and an 100ns initial access time. at 108mhz, the k8f5715e pro- vides an 7ns burst access time and an 100ns initial access time. at 133mhz, the k8f5715e provides an 6ns burst access time and an 100ns initial access time.the device performs a program operation in units of 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed with in typically 0.6sec. the device requires 25ma as program/erase current in the extended tem- perature ranges. the k8f56(57)15e nor flash memory is created by using samsung's advanced cmos proces s technology. this device is available in 44ball / 88 ball fbga package. features general description samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description pin name pin function a16 - a23 address inputs a/dq0 - a/dq15 multiplexed address/data input/output ce chip enable oe output enable reset hardware reset v pp accelerates programming we write enable wp hardware write protection input clk clock rdy ready output avd address valid input dpd deep power down vcc power supply v ss ground ? single voltage, 1.7v to 1.95v for read and write operations ? organization - 16,777,216 x 16 bit (word mode only) ? multiplexed data and address for reduction of interconnections - a/dq0 ~ a/dq15 ? read while program/erase operation ? multiple bank architecture - 16 banks (16mb partition) ? otp block : extra 512-word block ? read access time (@ c l =30pf) - asynchronous random access time : 100ns - synchronous random access time : 100ns - burst access time : 11ns (66mhz), 9ns(8 3mhz), 7ns (108mhz), 6ns(133mhz) ? burst length : - continuous linear burst - linear burst : 8-word & 16-word with no-wrap & wrap ? block architecture - four 16kword blocks and two hundreds fifty-five 64kword blocks - bank 0 contains four 16 kword blocks and fifteen 64kword blocks - bank 1 ~ bank 15 contain two hundred forty 64kword blocks ? reduce program time using the v pp ? support 32 words buffer program ? power consumption (typical value, c l =30pf) - synchronous read current : 35ma at 133mhz - program/erase current : 25ma - read while program/erase current : 45ma - standby mode/auto sleep mode : 30ua ? block protection/unprotection - using the software command sequence - last two boot blocks are protected by wp =v il - all blocks are protected by v pp =v il ? handshaking feature - provides host system with minimum latency by monitoring rdy ? erase suspend/resume ? program suspend/resume ? unlock bypass program/erase ? hardware reset (reset ) ? data polling and toggle bits - provides a software method of detecting the status of program or erase completion ? endurance 100k program/erase cycles minimum ? data retention : 10 years ? extended temperature : -25 c ~ 85 c ? support common flash memory interface ? low vcc write inhibit ? package : 88 - ball fbga type (8mm x 11mm), 0.8 mm ball pitch, 1.2mm (max.) thickness 44 - ball fbga type (8mm x 9mm), 0.5 mm ball pitch, 1.0mm (max.) thickness
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 5 88 ball fbga top view (ball down) du du nc wp vss vcc a20 rfu nc vss rfu clk nc a23 rfu nc rfu nc nc vcc du du nc nc dpd nc nc nc 12 3 45 6 7 8 a c d b a21 nc nc nc avd vpp nc rfu reset we nc a/dq7 a/dq13 a/dq5 a/dq10 a/dq2 rfu a/dq15 a/dq14 a/dq12 a/dq3 a/dq1 a16 a19 a17 a22 nc a18 rdy nc a/dq8 nc rfu oe a/dq6 a/dq4 a/dq11 a/dq9 rfu rfu rfu vccq v ss vss vccq vcc vss vss du du ce vcc a/dq0 vccq vccq rfu vss vss du du e g h f j l m k
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 6 functional block diagram vcc vss ce oe we wp reset rdy a16~a23 a/dq15 interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank 1 cell array bank 0 address bank 1 address bank 0 cell array avd a/dq0~ x dec y dec latch & control bank 15 cell array block inform vpp bank 15 address clk i/o dpd rdy a21 v ss clk v cc we a16 a20 avd a23 v ss a/dq7 a/dq6 a/dq13 a/dq12 a/dq3 a/dq15 a/dq14 v ss a/dq5 a/dq4 a/dq11 v cc reset v pp a19 a17 a22 wp a18 ce v ss a/dq2 a/dq9 a/dq8 oe a/dq10 v cc a/dq1 a/dq0 12345678910 a c d b 44 ball fbga top view (ball down)
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 7 table 2. k8f56(57)15e device bank divisions bank 0 bank 1 ~ bank 15 mbit block sizes mbit block sizes 16 mbit four 16kwords, fifteen 64kwords 240 mbit two hundred forty 64kwords ordering information k 8 f 56 1 5 e t m - f e 1f samsung nor flash memory device type mlc multiplexed burst operating temperature range c = commercial temp. (0 c to 70 c) e = extended temp. (-25 c to 85 c) block architecture t = top boot block b = bottom boot block version 1st generation access time refer to table 1 operating voltage range 1.7 v to 1.95v package s : fbga(lead free,osp) f : fbga d : fbga(lead free) organization x16 organization table 1-1. product classification speed/boot option top bottom 256mb for 66/83mhz k8f5615etm K8F5615EBM 256mb for 108/133mhz k8f5715etm k8f5715ebm density 56 = 256mbits for 66/83mhz 57 = 256mbits for 108/133mhz table 1. product line-up k8f56(57)15et mode speed option 1c (66mhz) 1d (83mhz) 1e (108mhz) 1f (133mhz) v cc =1.7v -1.95v synchronous/burst max. initial access time (t iaa, ns) 100 100 100 100 max. burst access time (t ba, ns) 11 9 7 6 asynchronous max. access time (t aa, ns) 100 100 100 100 max. ce access time (t ce, ns) 100 100 100 100 max. oe access time (t oe, ns) 15 15 15 15
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 8 table 3-1. k8f56(57)15etm device bank divisions (top boot block) bank quantity of blocks block size 0 4 16 kwords 15 64 kwords 1 16 64 kwords 2 16 64 kwords 3 16 64 kwords 4 16 64 kwords 5 16 64 kwords 6 16 64 kwords 7 16 64 kwords 8 16 64 kwords 9 16 64 kwords 10 16 64 kwords 11 16 64 kwords 12 16 64 kwords 13 16 64 kwords 14 16 64 kwords 15 16 64 kwords table 3-2. k8f56(57)15ebm device bank divisions (bottom boot block) bank quantity of blocks block size 15 16 64 kwords 14 16 64 kwords 13 16 64 kwords 12 16 64 kwords 11 16 64 kwords 10 16 64 kwords 9 16 64 kwords 8 16 64 kwords 7 16 64 kwords 6 16 64 kwords 5 16 64 kwords 4 16 64 kwords 3 16 64 kwords 2 16 64 kwords 1 16 64 kwords 0 15 64 kwords 4 16 kwords
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 9 table 4. device bus operations note : l=v il (low), h=v ih (high), x=don?t care. operation ce oe we a16-23 a/dq0-15 reset clk avd asynchronous read operation l l h add in add in/ d out hl write l h l add in add in / d in hl standby hxxxhigh-zhxx hardware reset xxxxhigh-zlxx load initial burst address l h h add in add in h burst read operation l l h x burst d out hh terminate burst read cycle hxxxhigh-zhxx terminate burst read cycle via reset xxxxhigh-zlxx terminate current burst read cycle and start new burst read cycle l h h add in add in h product introduction the k8f56(57)15e is an 256mbit (268,435,456 bits) nor-type burst flash memory. the device features 1.8v single voltage power supply operating within the range of 1.7v to 1.95v. the device is programmed by using the channel hot electron (che) injection mechanism which is used to program eprom s. the device is erased electrically by using fowler-nordhei m tunneling mechanism. to provide highly flexible eras e and program capability, the device adapts a block me mory architecture that divides its memory array into 259 blocks (64-kword x255, 16-kword x 4, ). programming is done in units of 16 bits (word). all bits of data in one or mul tiple blocks can be erased when the dev ice executes the erase operation. to prevent t he device from accidental erasing or over-writin g the programmed data, 259 memory blocks can be hardware protect ed. regarding read access time, at 66mhz, the k8f5615e pro- vides a burst access of 11ns with initial access times of 100ns at 30pf. at 83mhz, the k8f5615e provides a burst access of 9ns with initial access times of 100ns at 30pf. at 108mhz, the k8f5715e prov ides a burst access of 7ns wi th initial access times of 100n s at 30pf. at 133mhz, the k8f5715e provides a burst access of 6ns with initial access times of 100ns at 30pf. the command set of k8f56(57)15e is compatible with standard flas h devices. the device uses chip enable (ce ), write enable (we ), address valid(avd ) and output enable (oe ) to control asynchronous read and write operation. for burst operations, the device additionally requires ready (rdy) and clock (clk). device operations are executed by selective command codes. the command codes to be combined with addresses and data are sequentially written to the command registers using microproc essor write timing. the com- mand codes serve as inputs to an internal state machine which c ontrols the program/erase circuitr y. register contents also inte rnally latch addresses and data necessary to execute the program and eras e operations. the k8f56(57)15e is implemented with internal program/erase routines to execute the program/erase operations. the internal program/erase routines are invoked by program/ erase command sequences. the internal program routine automatica lly programs and verifies data at specified addresses. the internal erase routine automatically pre-programs the memory ce ll which is not programmed and t hen executes the erase operation . the k8f56(57)15e has means to indicate the status of completi on of program/erase operations. the status can be indicated via data polling of dq7, or the toggle bit (dq6). once the operations have been completed, the device automatically resets itself t o the read mode. the device requires only 35 ma as burst and asynchr onous mode read current and 25ma for buffer program/erase oper- ations.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 10 table 5. command sequences command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle asynchronous read add 1 ra data rd reset(note 5) add 1 xxxh data f0h autoselect manufacturer id(note 6) add 4 555h 2aah (da)555h (da)x00h data aah 55h 90h ech autoselect device id(note 6) add 4 555h 2aah (da)555h (da)x01h data aah 55h 90h note 6 autoselect block protection verify(note 7) add 4 555h 2aah (ba)555h (ba)x02h data aah 55h 90h 00h / 01h program add 4 555h 2aah 555h pa data aah 55h a0h pd unlock bypass add 3 555h 2aah 555h data aah 55h 20h unlock bypass program(note 8) add 2 xxx pa data a0h pd unlock bypass block erase(note 8) add 2 xxx ba data 80h 30h unlock bypass chip erase(note 8) add 2 xxxh xxxh data 80h 10h unlock bypass reset add 2 xxxh xxxh data 90h 00h chip erase add 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase add 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h erase suspend (note 9) add 1 (da)xxxh data b0h erase resume (note 10) add 1 (da)xxxh data 30h program suspend (note 11) add 1 (da)xxxh data b0h program resume (note 10) add 1 (da)xxxh data 30h block protection/unprotection (note 12) add 3 xxx xxx abp data 60h 60h 60h cfi query (note 13) add 1 (da)x55h data 98h command definitions the k8f56(57)15e operates by selecting and executing its operational modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. the defined valid register command sequences are stated in table 5.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 11 table 5. command sequences (continued) command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle write to buffer (note 14) add 3 555h 2aah ba ba pa wbl data aah 55h 25h wc pd pd program buffer to flash (note 14) add 1 ba data 29h write to buffer abort reset (note 15) add 3 555h 2aah xxx data aah 55h f0h set burst mode configuration register (note 16) add 3 555h 2aah note 17 data aah 55h c0h enter otp block region add 3 555h 2aah xxx data aah 55h 70h exit otp block region add 4 555h 2aah 555h xxx data aah 55h 75h 00h notes: 1. ra : read address , pa : program address, rd : read data, pd : program data , ba : block address (a23 ~ a14), da : bank a ddress (a23 ~ a20) abp : address of the block to be protected or unprotect ed , di :die revision id, cr : configuration register setting, wbl : write buffer location, wc : word count 2. the 4th cycle data of autoselect mode and rd are output data. the others are input data. 3. data bits dq15?dq8 are don?t care in comm and sequences, except for rd, pd and device id. 4. unless otherwise noted, address bits a23?a11 are don?t cares. 5. the reset command is required to return to read mode. if a bank entered the autoselect mode during the erase sus pend mode, writing the reset command returns that bank to the era se suspend mode. if a bank entered the autoselect mode during the program sus pend mode, writing the reset command returns that bank to the p rogram suspend mode. if dq5 goes high during the program or erase operation, wr iting the reset command returns that bank to read mode or erase s uspend mode if that bank was in erase suspend mode. 6. the 3rd and 4th cycle bank address of autoselect mode must be same. device id data : "2208h" for top boot block device, "2209h" for bottom boot block device 7. normal block protection verify : 00h for an unprotected block and 01h for a protected block. otp block protect verify (with otp block address after entering otp block) : 00h for unlocked, and 01h for locked. 8. the unlock bypass command sequence is required prior to this command sequence. 9. the system may read and program in non-erasing blocks when in the erase suspend mode. the system may enter the autoselect mode when in the erase suspend mode. the erase suspend command is valid only duri ng a block erase operation, and requires the bank address. 10. the erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address. 11. this mode is used only to enable data read by suspending the program operation. 12. set block address(ba) as either a6 = v ih , a1 = v ih and a0 = v il for unprotected or a6 = v il , a1 = v ih and a0 = v il for protected. 13. command is valid when the device is in read mode or autoselect mode. 14. for buffer program, firstly enter "write to buffer" command sequence and then enter block address and word count which is t he number of word data will be programmed. word count is smaller than the number of data wanted to program by one, example if 15 words need to be programmed wc (word count) should be 14. after entering command, enter pa/pd?s (program addresses/ program data). finally enter "progra m buffer to flash" command sequence, this starts a buffer program operation. this device supports 32 words buffer program. there is some caution points. - the number of pa/pd?s which are entered must be wc+1 - pa?s which are entered must be same a23~a5 address bits because buffer address is a2 3~a5 address and decided by pa e ntered firstly. - if pa which are entered isn?t same buffer address, then pa/pd which is entered may not be counted and not stored to bu ffer. - overwrite for program buffer is also prohibited. 15. command sequence resets device for next command after aborted write-to-buffer operation . 16. see "set burst mode configuration register" for details. 17. on the third cycle, the data should be "c0h", address bits a10-a0 should be 101_0101_0101b, and address bits a18-a11 set th e code to be latched.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 12 device operation the device has inputs/outputs that accept both address and dat a information. to write a command or command sequence (which includes programming data to the devic e and erasing blocks of memory), the system must drive clk, avd and ce to v il and oe to v ih when providing an address to the device, and drive clk, we and ce to v il and oe to v ih when writing commands or data. the device provide the unlock bypass mode to save its program time for program operation. unlike the standard program command sequence which is comprised of four bus cycles, only two program cycles are requir ed to program a word in the unlock bypass mode. one block, multiple blocks, or the entire device can be er ased. table 12 indicates the address space that each block occu pies. the device?s address space is divided into sixteen banks: bank 0 contains the boot/par ameter blocks, and the other banks(from b ank 1 to 15) consist of uniform blocks. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?bloc k address? is the address bits required to uniquely select a block. i cc2 in the dc characteristics table repr esents the active current specification for the write mode. the ac characteristics section contains ti ming specification tables and timi ng diagrams for write operation s. read mode the device automatically enters to asynchronous read mode after device power-up. no commands are required to retrieve data in asynchronous mode. after completing an internal program/erase r outine, each bank is ready to read array data. the reset com- mand is required to return a bank to the read(or erase-suspend-r ead)mode if dq5 goes high during an active program/erase opera- tion, or if the bank is in the autoselect mode. the synchronous(burst) mode will automatically be enabled on the first rising edge on the clk input while avd is held low. that means device enters from asynchronous read mode to burst read mode using clk and avd signal. when the burst read is termi- nated, the device return to asynchronous read mode automatically. asynchronous read mode for the asynchronous read mode a valid address should be assert ed on a/dq0-a/dq15 and a16-a23, while driving avd and ce to v il . we and oe should remain at v ih . note that clk must remain low for asynchronous read mode. the address is latched at the rising edge of avd , and then the system can drive oe to v il . the data will appear on a/dq0-a/dq15. since the memory array is divided into sixteen banks, each bank remains enabled for read acce ss until the command register contents are altered. address access time (t aa ) is equal to the delay from valid addresses to va lid output data. the chip enable access time(t ce ) is the delay from the falling edge of ce to valid data at the outputs . the output enable access time(t oe ) is the delay from the falling edge of oe to valid data at the output. the asynchronous access time is measured from a valid address, falling edge of avd or falling edge of ce whichever occurs last. to prevent the memory content from s purious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. synchronous (burst) read mode the device is capable of conti nuous linear burst operation and linear burst operation of a preset length. for the burst mode, t he sys- tem should determine how many clock cyc les are desired for the initial word(t iaa ) of each burst access and what mode of burst oper- ation is desired using "burst mode confi guration register" command sequences. see "set burst mode configuration" for further details. the status data also can be read by synchronous read mode with a bank address wh ich is programming or erasing. this st a- tus data by synchronous read mode can be output just once and t hen sychronous read mode will be terminated. refer to figure 8. to initiate the synchronous read again, a new address and avd pulse is needed after the host has completed status reads or the device has completed the program or erase operation. continuous linear burst read the synchronous(burst) mode will automatically be enabled on the first rising edge on the clk input while avd is held low. note that the device is enabled for asynchronous mode when it first powers up. the initial word is output t iaa after the rising edge of the first clk cycle. subsequent words are output t ba after the rising edge of each successive cl ock cycle, which automatically increments the internal address counter. note that the device has internal addres s boundary that occurs every 16 words. when the device is cro ss- ing the first word boundary, additional cl ock cycles are needed before data appears for the next address. the number of addtion al clock cycle can vary from zero to fourteen cycles, and the exact number of additional clock cycle depends on the starting address of burst read.(refer to figure 18) the rdy output indicates this condition to the system by pulsi ng low. the device will continue to out- put sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until th e system asserts ce high, reset low or avd low in conjunction with a new address.(see table 4.) the reset command does not ter- minate the burst read operation. when it accesses the bank is programming or erasi ng, continuous burst read mode will be termi- nated after status data output once. note that at least 10ns is needed to start next burst read operation from terminating previous burst read operation in the case of asserting ce high.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 13 8-, 16-word linear burst read as well as the continuous linear burst mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of words are read from consecutive addresses. in these modes, the addresses for burst r ead are determined by the group within whi ch the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode.(see table. 6) as an example: in wrap mode case, if the starting address in th e 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst sequence would be 2-3-4-5-6-7-0-1h. the burst sequence begins with the starti ng address written to the devic e, but wraps back to the first address in the selected group. in a similar manner, 16-word wrap m ode begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. in no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequenc e would be 2-3-4-5-6-7-8-9h. t he burst sequence begins with the starting address written to the de vice, and continue to the 8th address from starting address. i n a sim- ilar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th address from starting address. also, when the address cross the word boundary in no-wr ap mode, same number of additional clock cycles as continuous linear mode is needed. programmable wait state the programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after avd is driven from low to high for burst read mode. upon power up, the number of total initial access cycles defaults to fourteen. handshaking the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initia l cycle for optimal burst mode, the host should use the programma ble wait state configuration.(see "set burst mode configurati on register" for details.) the rising edge of rdy after oe goes low indicates the initial word of valid burst data. using the autoselect co mmand sequence the handshaking feature may be verified in the devi ce. set burst mode configuration register the device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. the burst mode configuration register mu st be set before the device enter burst mode. the burst mode configuration register is loaded with a three- cycle command sequences. on the third cycle, the data should be c0 h, address bits a10-a0 should be 101_0101_0101b, and address bits a18-a1 1 set the code to be latched. the device will power up or after a hardware reset with the default setting. table 6. burst address groups(wrap mode only) burst mode group size group address ranges 8 word 8 words 0-7h, 8-fh, 10-17h, .... 16 word 16words 0-fh, 10-1fh, 20-2fh, .... table 7. burst mode configuration register table address bit function settings(binary) a18 rdy active 1 = rdy active one clock cycle before data 0 = rdy active with data(default) a17 burst read mode 000 = continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011 = 8-word linear with no-wrap 100 = 16-word linear with no-wrap 101~111 = reserve a16 a15 a14 programmable wait state 0000 = data is valid on the 4th active clk edge after avd transition to v ih (40mhz) 0001 = data is valid on the 5th active clk edge after avd transition to v ih (50mhz) 0010 = data is valid on the 6th active clk edge after avd transition to v ih (54/60mhz) 0011 = data is valid on the 7th active clk edge after avd transition to v ih (66/70mhz) 0100 = data is valid on the 8th active clk edge after avd transition to v ih (80mhz) 0101 = data is valid on the 9th active clk edge after avd transition to v ih (83/90mhz) 0110 = data is valid on the 10th active clk edge after avd transition to v ih (100mhz) 0111 = data is valid on the 11th active clk edge after avd transition to v ih (108/110mhz) 1000 = data is valid on the 12th active clk edge after avd transition to v ih (120mhz) 1001 = data is valid on the 13th active clk edge after avd transition to v ih 1010 = data is valid on the 14th active clk edge after avd transition to v ih (default, at 133mhz) 1011 = data is valid on the 15th active clk edge after avd transition to v ih 1100~ 1111 = reserve a13 a12 a11 note: initial wait state should be set according to it?s clock frequency. table7 recommend the program wait state for each clock freq uencies. not 100% tested
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 14 programmable wait state configuration this feature informs the device the number of clock cycles that must elapse after avd is driven from low to high before data will be available. this value is determined by t he input frequency of the device. address bi ts a14-a11 determine the setting. (see burs t mode configuration register table) the programmable wait state setting instructs the device to se t a particular number of clock cycles for the initial access in burst mode. note that hardware reset will set the wait state to the default setting, that is 14 initial cycles. burst read mode setting the device supports five different burst r ead modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and 16 word linear burst modes with no-wrap. rdy configuration by default, the rdy pin will be hi gh whenever there is valid data on the output. the device can be set so that rdy goes active one data cycle before active data. adddress bit a18 determine this setting. the rdy pin behaves same way in word boundary crossing case. autoselect mode by writing the autoselect command sequences to the system, the device enters the autoselect mode. this mode can be read only by asynchronous read mode. the system can then read autoselect codes from the internal register(which is separate from the memory array). standard asynchronous read cycle timi ngs apply in this mode. the device offers the autoselect mode to identify manufact urer and device type by reading a binary code. in addition, this mode allows the host system to verify the block protection or unpro tection. table 5 shows the address and data requirements. the autose lect command sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program -suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the device. the autoselect co mmand sequence is initiated by first writin g two unlock cycles. this is followed by a third write cycle that contains the addr ess and the autoselect command. note that the bloc k address is needed for the verification of bloc k protection. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. and the burst read should be prohibited during autoselect mode. t o terminate the autoselect operation, write reset command(f0h) into the command register. standby mode when the ce inputs is held at v cc 0.2v, and the system is not reading or writing, t he device enters stand-by mode to minimize the power consumption. in this mode, the device outputs ar e placed in the high impedence state, independent of the oe input. when the device is in either of these standby modes , the device requires standard access time (t ce ) for read access before it is ready to read data. if the device is deselected during eras ure or programming, the device draws active current until the operation is complet ed. i cc5 in the dc characteristics table repres ents the standby current specification. table 8. burst address sequences start addr. burst address sequence(decimal) continuous burst 8-word burst 16-word burst wrap 0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -d-e-f 1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-0 1-2-3-4 ... -e-f-0 2 2-3-4-5-6-7-8... 2-3-4-5-6-7-0-1 2-3-4-5 ... -f-0-1 . . . . . . . . no-wrap 0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -d-e-f 1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-8 1-2-3-4 ... -e-f-10 2 2-3-4-5-6-7-8... 2-3-4-5-6-7-8-9 2-3-4-5 ... -f-10-11 . . . . . . . . table 9. autoselect mode description description address read data manufacturer id (da) + 00h ech device id (da) + 01h 2208h(top boot block), 2209h(bottom boot block) block protection/unprotection (ba) + 02h 01h (protected), 00h (unprotected)
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 15 automatic sleep mode the device features automatic sleep mode to minimize the device power consumption duri ng both asynchronous and burst mode. when addresses remain stable for t aa +60ns, the device automatically enables this mode. the automatic sleep mode is depends on the ce , we and oe signal, so ce , we and oe signals are held at any state. in a sl eep mode, output data is latched and always available to the system. when oe is active, the device provides new data without wait time. automatic sleep mode current is equal to standby mode current. output disable mode when the oe input is at v ih , output from the device is disabled. th e outputs are placed in the high impedance state. block protection & unprotection to protect the block from accidental wr ites, the block protection/unprotection comm and sequence is used. on power up, all block s in the device are protected. to unprotect a block, the system must write the block protection/unprotection command sequence. the f irst two cycles are written: addresses are don?t care and data is 60h. using the third cycle, the block address (abp) and command (6 0h) is written, while specifying with addresses a6, a1 and a0 whether that block should be protected (a6 = v il, a1 = v ih , a0 = v il ) or unprotected (a6 = v ih, a1 = v ih , a0 = v il ). after the third cycle, the system can cont inue to protect or unprotect additional cycles, or exit the sequence by writing f0h (reset command). the device offers three types of data protection at the block level: ? the block protection/unprotection comm and sequence disables or re-enables both pr ogram and erase operations in any block. ? when wp is at v il , the two outermost blocks are protected. ? when v pp is at v il , all blocks are protected. note that user never float the v pp and wp , that is, vpp is always connected with v ih , v il or v id and wp is v ih or v il . hardware reset the device features a hardware method of resetting the device by the reset input. when the reset pin is held low(v il ) for at least a period of trp, the device immediately te rminates any operation in progress, trista tes all outputs, and ignores all read/write com- mands for the duration of the reset pulse. the device also resets the internal state machine to asynchronous read mode. to ensure data integrity, the interrupted operation should be reinitia ted once the device is ready to accept another command seque nce. as previously noted, when reset is held at vss 0.2v, the device enters standby mode. the reset pin may be tied to the system reset pin. if a system reset occurs during the internal program or erase routine, the device will be automatically reset to the asyn- chronous read mode; this will enable the systems microprocesso r to read the boot-up firmware from the flash memory. if reset is asserted during a program or erase operation, the device requires a time of tready (during internal routines) before the device is ready to read data again. if reset is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tready (not during internal routines). trh is needed to read data after reset returns to v ih . refer to the ac char- acteristics tables for reset parameters and to figure 10 for the timing diagram. software reset the reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. the addresses are in don?t care state. the reset command ma y be written between the sequence cycles in an erase command sequence before erasing begins, or in an program command sequenc e before programming begins. if the device begins erasure or programming, the reset command is ignored unt il the operation is completed. if the program command sequence is written to a ban k that is in the erase suspend mode, writing the reset command re turns that bank to the erase-suspend-read mode. the reset com- mand valid between the sequence cycles in an autoselect co mmand sequence. in an autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autos elect mode while in the erase suspend mode, writing the reset co m- mand returns that bank to the erase-suspend-read mode. also, if a bank entered the autoselect mode while in the program suspend mode, writing the reset command returns that bank to the progr am-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in erase suspend) program the k8f56(57)15e can be programmed in units of a word. programming is writing 0's into the memory array by executing the inter - nal program routine. in order to perform the internal program routine, a four-cycle command s equence is necessary. the first tw o cycles are unlock cycles. the third cycle is assigned for the progr am setup command. in the last cycle, the address of the memo ry location and the data to be programmed at that location are wri tten. the device automatically generates adequate program pulses and verifies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not required to provide further controls or timings. during the inte rnal program routine, commands written to the device will be ig nored. note that a hardware reset during a program operation wi ll cause data corruption at the corresponding location.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 16 accelerated program the device provides accelerated program operations through t he vpp input. using this mode, fa ster manufacturing throughput at t he factory is possible. when v id is asserted on the vpp input, the device automatica lly enters the unlock bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to r educe the time required for program operations. i n accelerated program mode, the system would use a two-cycle program command sequence for only a word program. by removing v id returns the device to normal operation mode. note that read while accelerated program and program suspend mode are not guaranteed. ? program/erase cycling must be limite d below 100cycles for optimum performance. ? ambient temperature requirements : t a = 30 c10 c single word accelerated program operation the system would use two-cycle program sequence (one-cycle (xxx - a0h) is for single word program command, and next one- cycle (pa - pd) is for program address and data) writer buffer programming write buffer programming allows the system write to a maximum of 32 words in one programming operation. this results in faster effective programming time than the standar d programming algorithms. the write buff er programming command sequence is initi- ated by first writing two unlock cycles. this is followed by a third write cy cle containing the write buffer load command writt en at the block address in which programming will occur. the fourth cycle writes the block address and the number of word locations, minu s one, to be programmed. for example, if the system will progr am 19 unique address locations, then 12h should be written to the device. this tells the device how many writ e buffer addresses will be loaded with data. the number of locations to program cann ot exceed the size of the write buffer or the operation will abor t. the fifth cycle writes the first address location and data to be pro- grammed. the write-buffer-page is selected by address bits a23(max.) ~ a5 entered at fifth cycle . all subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit a23(max.) ~ a5 as those entered at fifth cycle. write buffer locations may be loaded in any order. once the specified number of write buffer locations have been load ed, the system must then write the "program buffer to flash" com mand at the block address. any other command address/data combination aborts the write buffer programming operation. the device then begins programming. data polli ng should be used while monitoring the last address location loaded into the write bu ffer. dq7, dq6, dq5, and dq1 should be monitored to determine the dev ice status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to ex ecute the next command. note also that an address loaction can - not be loaded more than once into the write-buffer-page. the write buffer programming sequence can be aborted in the following ways: ? loading a value that is greater than the buffer size(32-words) during then number of word locations to program step. (in case, wc > 1fh @table5 ) ? the number of program address/data pairs entered is different to the number of word locations initially defined with wc (@tab le5) ? writing a program address to have a different write-buffer-page with selected write-buffer-page ( address bits a23(max) ~ a5 are different) ? writing non-exact "program buffer to flash" command the abort condition is indicated by dq1 = 1, dq7 = data (for the last address location loaded), dq6 = toggle, and dq5=0. a "write- to-buffer-abort reset" command sequence must be written to reset t he device for the next operation. note that the third cycle o f write-to-buffer-abort reset command sequence(xxxh-f0h) is requir ed when using write-buffer-programming features in unlock bypass mode. and from the third cycle to the last cycle of write to buffer command is also required when using write-buffer-pro - gramming features in unlock bypass mode. a bit cannot be programm ed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was succ essful. however, a succeeding re ad will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1." accelerated write buffer programming the device provides accelerated write buffer program operations through the vpp input. using this mode, faster manufacturing throughput at the factory is possible. when v id is asserted on the vpp input, the device te mporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time requir ed for program operations. in accelerated write buffer progra m mode, the system must enter "write to buffer" and "program bu ffer to flash" command sequence to be same as them of normal write buffer programming and only can reduce the program time. note that the third cycle of "write to buffer abort reset" comma nd sequence(xxxh-f0h) is required to reset the device for the next operation in an accelerated mode. note that read while accelerated write buffer program and program suspend mode are not guaranteed. ? program/erase cycling must be limite d below 100cycles for optimum performance.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 17 chip erase to erase a chip is to write 1 s into the entire memory array by executing the inte rnal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is written after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the internal erase routine automatic ally pre-programs and verifies t he entire memory for an all zero data pattern prior to erasi ng. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when dq7 is "1". after that the device returns to the read mode. block erase to erase a block is to write 1 s into the desired memory block by executing the in ternal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 5. after the first two "unlock" cycles, the erase setup command (80h) i s written at the third cycle. then there are tw o more "unlock" cycles followed by the bl ock erase command. the internal erase rou tine automatically pre-programs and verifies the entire memory prio r to erasing it. the block addr ess is latched on the rising edge of avd , while the block erase command is latched on the rising edge of we . multiple blocks can be erased sequentially by writing the sixth bus-cycle. upon completion of the last cy cle for the block erase, additional block address and the block erase command (30h) ca n be written to perform the multi-block erase. for the multi-bl ock erase, only sixth cycle(bloc k address and 30h) is needed.(simi larly, only second cycle is needed in unlock bypass block erase.) an 50us (typical) "time window" is required between the block erase command writes. the block erase command must be written with in the 50us "time window", otherwise the block erase command will be ignored. the 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time window" to latch the block erase command. during the 50us of "time window", any co mmand other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50 us of "time window", the block erase command will initia te the internal erase routine to erase the selected blocks. any block erase address and command follo wing the exceeded "time window" may or may not be accepted. no other commands will be rec ognized except the erase suspend command during block erase oper- ation. the device provides accelerated erase o perations through the vpp input. when v id is asserted on the vpp input, the device auto- matically enters the unlock bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. by removing v id returns the device to normal operation mode. unlock bypass the k8f56(57)15e provides the unlock bypass mode to save its oper ation time. this mode is possibl e for program, block erase and chip erase operation. there are two methods to enter the unlock bypass mode. the mode is invoked by the unlock bypass command sequence or the assertion of v id on v pp pin. unlike the standard program/erase comm and sequence that contains four bus cycles, the unlock bypass program/erase command sequence comprises onl y two bus cycles. the unlock bypass mode is engaged by issu- ing the unlock bypass command sequenc e which is comprised of three bus cycles. writing first two unl ock cycles is followed by a third cycle containing the unlock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass pro- gram/erase command sequence is necessary. the unlock bypass pr ogram command sequence is compri sed of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the program address and data. this command sequence is the only valid one for programming the device in the unlock bypass m ode. also, the unlock bypass erase command sequence is com- prised of two bus cycles; writing the unloc k bypass block erase command(80h-30h) or wr iting the unlock bypass chip erase com- mand(80h-10h). this command sequences are the only valid ones fo r erasing the device in the unl ock bypass mode. the unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. the unlock bypass reset command sequence consists of two bus cycles. the first cycle must contain the data (90h ). the second cycle contains only the da ta (00h). then, the device returns to the read mode. to enter the unlock bypass mode in hardware level, the v id also can be used. by assertion v id on the v pp pin, the device enters the unlock bypass mode. also, the all blocks are te mporarily unprotected when the device using the v id for unlock bypass mode. to exit the unlock bypass mode, just remove the asserted v id from the v pp pin.(note that user never float the v pp , that is, vpp is always connected with v ih , v il or v id . ) . erase suspend / resume the erase suspend command interrupts the block erase to read or progr am data in a block that is not being erased. also, it is p os- sible to protect or unprotect of the block that is not being er ased in erase suspend mode. the erase suspend command is only va lid during the block erase operation including the time window of 50 us. the erase suspend command is not valid while the chip eras e or the internal program routine sequence is running. when the erase suspend command is written during a block erase operation, the device requires a maximum of 20 us(recovery time) to suspend t he erase operation. therefore system must wait for 20us(recov - ery time) to read the data from the bank which include the bl ock being erased. otherwise, system can read the data immediately from a bank which don?t include the block being erased without re covery time(max. 20us) after erase suspend command. and, after the maximum 20us recovery time, the devic e is availble for programming data in a block that is not being erased. but, when the erase suspend command is written during the bl ock erase time window (50 us) , the devic e immediately terminates the block erase time window and suspends the erase operation. the system may also write the autoselect command sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase oper ation will resume. when the erase suspend or erase resume command is execut ed, the addresses are in don't care state. in erase suspend followed by resume operation, min. 200ns is needed for checking t he busy status.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 18 program suspend / resume the device provides the program suspend/r esume mode. this mode is used to enable data read by suspending the program operation. the device accepts a program suspend command in program mode(including program operations performed during erase suspend) but other commands are ignored. after input of the program suspend command, 5us is needed to enter the pro- gram suspend read mode. therefore system must wait for 5us(r ecovery time) to read the data from the bank which include the block being programmed. otherwise, system can read the data immediately from a bank which don't include block being pro- grammed without recovery time(max. 5us) after program sus pend command. like an erase suspend mode, the device can be returned to program mode by using a program resume command. in the program suspend mode, protect/unprotect command is prohibited. in program suspend followed by resume operation, min. 200ns is needed for checking the busy status. read while write operation the device is capable of reading data from o ne bank while writing in the other banks. this is so called the read while write o pera- tion. an erase operation may also be suspended to read from or pr ogram to another location within the same bank(except the bloc k being erased). the read while write operation is prohibited during the chip erase operation. figure 17 shows how read and write cycles may be initiated for simultaneous operation with zero lat ency. refer to the dc characteristics table for read-while-writ e current specifications. otp block region the otp block feature provides a 512-word flash memory regi on that enables permanent part i dentification through an electronic serial number (esn). the otp block is customer lockable and sh ipped with itself unlocked, allowing customers to untilize the th at block in any manner they choose. the custom er-lockable otp block has the protection ve rify bit (dq0) set to a "0" for unlocked state or a "1" for locked state. the system accesses the otp block through a command sequence (see "enter otp block / exit otp block command sequence" at table 5). after the system has written the "enter otp bl ock" command sequence, it may r ead the otp block by using the addresses (ffff80h~ffffffh) normally and may check the protection ve rify bit (dq0) by using the "autoselect block protection verify" command sequence with otp block address. this mode of operation continues until the system issues the "exit otp block" command suquence, a hardware reset or until pow er is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to main blocks. note that the accelerated functi on and unlock bypass modes are not available when the otp block is enabled. customer lockable in a customer lockable device, the otp block is one-time programm able and can be locked only once. note that the accelerated function and unlock bypass functions are not available when programming the otp bloc k. locking operation to the otp block is started by writing the "enter otp block" command sequence, and then the "block protection" command sqeunce (table 5) with an otp block address. "exit otp block" co mmnad sequence makes exiting from otp block . the locking operation has to be above 100us. "exit otp block" commnad s equence and hardware reset makes locking operat ion finished and then exiting from otp block. the otp block lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the otp block space can be modified in any way. the otp block access is prohibited during program or erase suspend mode. low v cc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for vcc less than v lko . if the vcc < v lko (lock-out voltage), the command register and all internal progr am/erase circuits are disabl ed. under this condition the device will reset itself to the read mode.subsequent writ es will be ignored until the vcc level is greater than v lko . it is the user?s responsibility to ensure that the contro l pins are logically correct to prevent unintentional writes when vcc is above v lko. write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe , ce, avd or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a log- ical zero while oe is a logical one.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 19 dq7 : data polling when an attempt to read the device is made while executing the in ternal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is co mpleted an attempt to access to the device will produce the tru e data written to dq7. when a user attempts to read the block being er ased, dq7 will be low. if the dev ice is placed in the erase/prog ram suspend mode, the status can be detected via the dq7 pin. if the system tries to read an address which belongs to a block that is being erase suspended, dq7 will be high. and, if the system tries to read an address which belongs to a block that is being pro gram suspended, the output will be the true data of dq7 itself. if a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement dat a in approximately 100us and the device then returns to the read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop after the device completes its internal routine. if the device is in the erase/program suspend mode, an attempt to read an address that belongs to a block that is being erased or programmed w ill produce a high output of dq 6. if an address belongs to a block that is not being erased or progr ammed, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected bl ock, dq6 toggles for approxim ately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing the data in the block. flash memory status flags the k8f56(57)15e has means to indicate its status of operati on in the bank where a program or erase operation is in processes. address must include bank address being executed internal routine op eration. the status is indica ted by raising the device stat us flag via corresponding dq pins. the status data can be read during burst read mode by using avd signal with a bank address. that means status read is supported in synchronous mode. if status r ead is performed, the data provided in the burst read is identic al to the data in the initial access. to initiate the synchronous read again, a new address and avd pulse is needed after the host has completed status reads or the device has completed the program or erase operation. the corresponding dq pins are dq7, dq6, dq5, dq3, dq2 and dq1. table 10. hardware sequence flags notes : 1. dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. 3. note that dq7 during write-to-buffer-programming indicates the data-bar for dq7 data for the last loaded write-buffer address location. status dq7 dq6 dq5 dq3 dq2 dq1 in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1100 toggle (note 1) 0 erase suspend read non-erase suspended block data data data data data data erase suspend program non-erase suspended block dq7 toggle 0 0 1 0 program suspend read program suspended block dq7 1 0 0 toggle (note 1) 0 program suspend read non- program suspended block data data data data data data exceeded time limits programming dq7 toggle 1 0 no toggle 0 block erase or chip erase 0 toggle 1 1 (note 2) 0 erase suspend program dq7 toggle 1 0 no toggle 0 write-to- buffer (note3) busy state dq7 toggle 0 0 no toggle 0 exceeded timing limits dq7 toggle 1 0 no toggle 0 abort state dq7 toggle 0 0 no toggle 1
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 20 dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time win- dow expires. in this case, the internal erase routine will init iate the erase operation.therefore, the device will not accept f urther write commands until the erase operation is complete d. dq3 is low if the block erase time wi ndow is not expired. within the block era se time window, an additional block erase comm and (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq 2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase rout ine, dq2 toggles only if an erasing block is read. although the internal erase routi ne is in the exceeded time limits, dq2 toggles on ly if an erasing block in the exceeded time limits is read. when the device is in th e erase/program suspend mode, dq2 toggles only if an address in t he erasing or programming block is read. if a non-erasing or non - programmed block address is read during the erase/program suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend blo ck while the device is in the erase suspend mode. dq1 : buffer program abort indicator dq1 indocates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a "1". the system must issue the write-to-buffer-abort-reset command sequenc e to return the device to reading array data. rdy: ready normally the rdy signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. if rdy is low state, data is not valid at expected time, and if high state, data is valid. note that, if ce is low and oe is high, the rdy is high state. start dq7 = data ? no dq5 = 1 ? fail pass yes figure 1. data polling algorithms figure 2. toggle bit algorithms dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes yes read(dq0~dq7) valid address
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 21 deep power down in order to reduce the power consumption of the device, it shall a deep power down mode inplemented on a seperate pin. the deep power down mode is active when the deep power down signal is acti vated, high state. in deep power down the device shall turn of f all circuitry in order to reach a power c onsumption of 2ua(tpy). the device shall exit the deep power down mode within 75us aft er that the deep power down signal has been de-activated, set to lo w. in deep power down the state of the device chip select shall have no impact on the device power consumption. all pr ogramming capabilities of the device are inhibited. at the power up, the device shall accept any order of activati on of the reset and deep power down signal. the devi ce shall resp ond within the specified time for the signal that was deactivated/activated lates t. the deep power down mode is activated when dpd pin high state only. if dpd is asserted during a program or erase ope ration, the device requires a time of tdp(during internal rout ines) before the device is ready to enter dpd mode. figure 3. dpd timings t wkup ce , oe dpd t dp t wkup ce , oe reset timings not during internal routines reset timings during internal routines deep power down (dpd) note: not 100% tested. parameter symbol all speed options unit min typ max dpd pin high(not during internal routines) to dpd mode (note) t dp 100 - - ns dpd pin high(during internal routines) to dpd mode (note) t dp 20 - - s dpd low time before read (note) t wkup 75 - - s switching waveforms t dp dpd
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 22 commom flash memory interface common flash momory interface is contrived to increase the compatibility of host syst em software. it provides the specific inf orma- tion of the device, such as memory size and electrical features. once this informat ion has been obtained, the system software w ill know which command sets to use to enable flash wr ites, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h , the device enters the cfi mode. and then if the system writes the address shown in table 11, the system can read the cfi data. q uery data are always presented on the lowest-order data out- puts(dq0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command. table 11. common flash memory interface code description addresses (word mode) data query unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h primary oem command set 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 0000h 0000h address for alternate oem ex tended table (00h = none exists) 19h 1ah 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 0017h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0019h vpp(acceleration program) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1dh 0085h vpp(acceleration program) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1eh 0095h typical timeout per single word write 2 n us 1fh 0008h typical timeout for max buffer write 2 n us(00h = not supported) 20h 0009h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 0012h max. timeout for word write 2 n times typical 23h 0001h max. timeout for buffer write 2 n times typical 24h 0001h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 0000h device size = 2 n byte 27h 0019h flash device interface description 28h 29h 0000h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0006h 0000h number of erase block r egions within device 2ch 0002h
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 23 table 11. common flash memory interface code (continued) * max. operating clock frequency : data is 53h in 66/83mhz part (k8f5615et(b)m) description addresses (word mode) data erase block region 1 information bits 0~15: y+1=block number bits 16~31: block size= z x 256bytes 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 2 information 31h 32h 33h 34h 00feh 0000h 0000h 0002h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0030h minor version number, ascii 44h 0030h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 0002h block protect 00 = not supported, 01 = supported 47h 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 0000h block protect/unprotect scheme 00 = not supported, 01 = supported 49h 0001h simultaneous operation 00 = not supported, 01 = supported 4ah 0001h burst mode type 00 = not supported, 01 = supported 4bh 0001h page mode type 00 = not supported, 01 = 4 word page 02 = 8 word page 4ch 0000h top/bottom boot block flag 02h = bottom boot device, 03h = top boot device 4dh 0003h max. operating clock frequency (mhz )* 4eh 0085h rww(read while write) functionality restrictio n (00h = non exists , 01h = exists) 4fh 0000h handshaking 00 = not supported at both mode, 01 = supported at sync. mode 10 = supported at async. mode, 11 = supported at both mode 50h 0001h
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 24 absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during tr ansitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage is vcc+0.6v on input / output pins whic h, during transitions, may overshoot to vcc+2.0v for periods <20n s. 2. minimum dc input voltage is -0.5v on v pp . during transitions, this level may fall to -2.0v for periods <20ns. maximum dc input voltage is +9.5v on v pp which, during transitions, may ov ershoot to +12.0v for periods <20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. ex posure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +2.5 v v pp v in -0.5 to +9.5 all other pins -0.5 to +2.5 temperature under bias commercial t bias -10 to +125 c extended -25 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma operating temperature t a (commercial temp.) 0 to +70 c t a (extended temp.) -25 to + 85 c dc characteristics parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc , v cc =v ccmax - 1.0 - + 1.0 a vpp leakage current i lip v cc =v ccmax , v pp =9.5v - - 35 a output leakage current i lo v out =v ss to v cc , v cc =v ccmax , oe =v ih - 1.0 - + 1.0 a active burst read current i ccb1 ce =v il , oe =v ih 66mhz - 30 55 ma active asynchronous read current i cc1 ce =v il , oe =v ih 10mhz - 35 55 ma 1mhz - 8 10 ma active write current (note 2) i cc2 ce =v il , oe =v ih , we =v il , v pp =v ih -2540ma read while write current i cc3 ce =v il , oe =v ih -4570ma accelerated program current i cc4 ce =v il , oe =v ih , v pp =9.5v - 15 30 ma standby current i cc5 ce = reset =v cc 0.2v - 30 110 a standby current during reset i cc6 reset = v ss 0.2v - 30 110 a automatic sleep mode(note 3) i cc7 ce =v ss 0.2v, other pins=v il or v ih v il = v ss 0.2v, v ih = v cc 0.2v -30110 a deep power down mode i cc8 -220 a input low voltage v il -0.5 - 0.4 v input high voltage v ih v cc -0.4 - v cc +0.4 v output low voltage v ol i ol = 100 a , v cc =v ccmin - - 0.1 v output high voltage v oh i oh = -100 a , v cc =v ccmin v cc -0.1 - - v voltage for accelerated program v id 8.5 9.0 9.5 v low v cc lock-out voltage v lko 1.0 - - v vpp current in program/erase ivpp vpp = 9.5v - 0.8 5 ma vpp = 1.95v - - 50 a recommended operating conditions ( voltage reference to gnd ) parameter symbol min typ. max unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 000v notes : 1. maximum icc specifications are tested with vcc = vccmax. 2. icc active while internal erase or internal program is in progress. 3. device enters automatic sleep mode when addresses are stable for taa + 60ns.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 25 ac test condition parameter value input pulse levels 0v to v cc input rise and fall times 5ns @66mhz, 5ns @80mhz, 1ns @133mhz input and output timing levels v cc /2 output load c l = 30pf 0v v cc v cc /2 v cc /2 input pulse and test point input & output test point capacitance (t a = 25 c, v cc = 1.8v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 4 pf output capacitance c out v out =0v - 6 pf control pin capacitance c in2 v in =0v - 4 pf output load device under te s t * c l = 30pf including scope and jig capacitance ac characteristics synchronous/burst read note: not 100% tested. parameter symbol 1c (66 mhz) 1d (83 mhz) 1e (108 mhz) 1f (133 mhz) unit min max min max min max min max initial access time t iaa - 100 - 100 - 100 - 100 ns burst access time valid clock to output delay t ba -11 - 9 - 7 - 6ns avd setup time to clk t avds 5 - 4 - 4 - 2.5 - ns avd hold time from clk t avdh 2- 2 - 2 - 2 -ns avd high to oe low t avdo 0- 0 - 0 - 0 -ns address setup time to clk t acs 5 - 4 - 4 - 2.5 - ns address hold time from clk t ach 6- 5 - 2 - 2 -ns data hold time from next clock cycle t bdh 3- 3 - 2 - 2 -ns output enable to rdy valid t oer -11 - 9 - 7 - 6ns ce disable to high z t cez - 15 - 15 - 15 - 15 ns oe disable to high z t oez - 15 - 15 - 15 - 15 ns ce setup time to clk t ces 6- 6 - 6 - 6 -ns clk to rdy setup time t rdya -11 - 9 - 7 - 6ns rdy setup time to clk t rdys 3- 3 - 2 - 2 -ns clk high or low time t clkh/l 3.5 - 3 - 2.5 - 2.5 - ns clk fall or rise time t clkhcl -3-3-2- 1ns
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 26 switching waveforms note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n ce clk avd oe a/dq0: a/dq15 rdy aa aa figure 4. continuous burst mode read (133 mhz) a16-a23 da+3 t rdys 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 7.5 ns typ. t avdo t rdya figure 5. 8 word linear burst mode with wrap around (133 mhz) note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n aa aa da+3 t rdys 7.5ns typ(133mhz). da+4 da+5 da+6 ce clk avd oe a/dq0: a/dq15 rdy a16-a23
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 27 figure 6. 8 word linear burst mode with rdy set on e cycle before data (wrap around, cr setting : a18=1) note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. switching waveforms 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n aa aa da+3 t rdys 7.5ns typ(133mhz). da+4 da+5 da+6 ce clk avd oe a/dq0: a/dq15 rdy a16-a23 t rdya figure 7. 8 word linear burst mode (no wrap case) note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 t ces t avds t avdh t acs t ach t iaa t oer t ba t bdh t cez t oez hi-z hi-z hi-z d7 d8 d9 d14 aa aa d10 t rdys 7.5ns typ(133mhz). d11 d12 d13 ce clk avd oe a/dq0: a/dq15 rdy a16-a23
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 28 switching waveforms figure 8. synchronous status data read mode note: in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 t ces t avds t avdh t acs t ach t iaa t oer t cez t oez hi-z hi-z hi-z aa aa t rdys 7.5ns typ(133mhz). ce clk avd oe a/dq0: a/dq15 rdy a16-a23
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 29 ac characteristics switching waveforms t oe va va valid rd t ce t oeh t oez t aavdh t avdp t aavds ce oe we a/dq0: avd a/dq15 a16-a23 asynchronous mode read (tce) hi-z hi-z rdy asynchronous read note: not 100% tested. parameter symbol 1c 1d 1e 1f unit min max min max min max min max access time from ce low t ce - 100 - 100 - 100 - 100 ns asynchronous access time t aa - 100 - 100 - 100 - 100 ns avd low time t avdp 12-10-8-7-ns address setup time to rising edge of avd t aavds 5-4-4-2.5-ns address hold time from rising edge of avd t aavdh 2-2-2-2-ns output enable to output valid t oe - 15 - 15 - 15 - 15 ns output enable hold time read t oeh 0-0-0-0-ns toggle and data polling 10 - 10 - 10 - 10 - ns output disable to high z(note) t oez - 15 - 15 - 15 - 15 ns
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 30 t oe va va valid rd t oeh t oez t aa t aavdh t avdp t aavds ce oe we a/dq0: avd a/dq15 a16-a23 t oe va va valid rd t oeh t oez t aa t aavdh t avdp t aavds ce oe we a/dq0: avd a/dq15 a16-a23 figure 9. asynchronous mode read note: va=valid read address, rd=read data. asynchronous mode read (taa) case 1 : valid address transition occurs before avd is driven to low case 2 : valid address transition occurs after avd is driven to low hi-z hi-z rdy hi-z hi-z rdy asynchronous mode may not support read foll owing four sequential invalid read condition within 200ns.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 31 ac characteristics figure 10. reset timings t rh ce , oe reset t rp t ready t ready ce , oe reset t rp reset timings not during internal routines reset timings during internal routines hardware reset(reset ) note: not 100% tested. parameter symbol all speed options unit min max reset pin low(during internal routines) to read mode (note) t ready -20 s reset pin low(not during internal routines) to read mode (note) t ready - 500 ns reset pulse width t rp 200 - ns reset high time before read (note) t rh 200 - ns reset low to standby mode t rpd 20 - s switching waveforms
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 32 erase/program operation notes: 1. not 100% tested. 2. internal programming algorithm is optimized for buffer program, so normal word programming or single word buffer program use buffer program algorithm. 3. internal programming algorithm for supporting accelerated mode uses a method to double the number of words programmed simultaneously. 4. typical 32-words buffer program time pays due regard to that each program data pattern ("11", "10". "01", "00") has a same portion in 32 words buffer. parameter symbol all speed options unit min typ max we cycle time(note 1) t wc 100 - - ns address setup time t as 5--ns address hold time t ah 7--ns avd low time t avpd 12 - - ns data setup time t ds 60 - - ns data hold time t dh 0--ns read recovery time before write t ghwl 0 - -ns ce setup time t cs 0--ns ce hold time t ch 0--ns we high to avd low t wea 30 - - ns we pulse width t wp 60 - - ns we pulse width high t wph 40 - - ns latency between read and write operations t sr/w 0--ns word programming operation (note 2) t pgm -80- s single word buffer program (note 2) t pgm_bp -80- s 32 words buffer program (note 4) t pgm_bp - 320 - s accelerated programming operation (note 3) t accpgm -80- s accelerated single word buffer program (note 3) t accpgm_bp -80- s accelerated 32 words buffer program (note 4) t accpgm_bp - 128 - s block erase operation t bers -0.6-sec v pp rise and fall time t vpp 500 - - ns v pp setup time (during accelerated programming) t vps 1-- s v cc setup time t vcs 50 - - s ac characteristics
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 33 erase/program performance notes: 1. 25 c, v cc = 1.8v, 100,000 cycles, typical pattern. 2. system-level overhead is defined as the ti me required to execute the two or four bus cycle command necessary to program each word. in the preprogramming step of the internal er ase routine, all words are programmed to 00h before erasure. 3. 100k program/erase cycle in all bank parameter limits unit comments min. typ. max. block erase time 64 kword - 0.6 3.0 sec includes 00h programming prior to erasure 16 kword - 0.3 1.5 chip erase time - 154 771 accelerated block erase time 64 kword - 0.4 3.0 16 kword - 0.2 1.5 accelerated chip erase time - 103 771 word programming time - 80 550 s / word excludes system level over- head 32 words buffer programming time - 10 32 accelerated word programming time - 80 550 accelerated 32 words buffer programming time - 4 22 chip programming time - 168 537 sec accelerated chip programming time - 68 370
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 34 program command sequence (last two cycles) avd a16:a23 we ce clk t avdp t as t ah t ds t dh t ch t wp t cs t wph t wc t pgm t vcs pa va va va va in progress complete pd pa a0h 555h a/dq0: a/dq15 oe v cc read status data notes: 1. pa = program address, pd = program data , va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a16?a23 are don?t care dur ing command sequence unlock cycles. 4. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. figure 11. program operation timing switching waveforms v il program operations t wea
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 35 notes: 1. ba = block address, wc = word count, pa = program address, pd = program data, va = valid address for reading status bits. 2. sequential pa_1, pa_2, ... , pa_n must have same address bits a23(max.) ~ a5 as pa_0 entered firstly 3. the number of program/data pairs entered must be same as wc+1 because wc = n. 4. ?in progress? and ?complete? refer to status of program operation. 5. a16?a23 are don?t care dur ing command sequence unlock cycles. 6. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. figure 12. buffer pr ogram operation timing switching waveforms buffer program operations avd a16:a23 we ce clk t avdp t as t ah t ds t wp t cs t wph t wc t vcs aah 555h a/dq0: a/dq15 oe v cc v il 55h 2aah 25h ba wc ba pd_0 pa_0 pd_1 pa_1 pd_n pa_n 29h ba ba ba pa_0 pa_1 pa_n ba t pgm_bp buffer program command sequence word count program address/data pairs (wc+1) "buffer to flash"
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 36 erase command sequence (last two cycles) avd a16:a23 we ce t avdp t as t ah t ds t dh t ch t bers t vcs ba va va va va in progress complete 30h ba 55h 2aah a/dq0: a/dq15 oe v cc read status data notes: 1. ba is the block address for block erase. 2. address bits a16?a23 are don?t cares duri ng unlock cycles in the command sequence. 3. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. figure 13. chlp/block erase operations switching waveforms 555h for chip erase 10h for chip erase t wp t cs t wph t wc clk v il erase operation t wea
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 37 switching waveforms figure 14. unlock bypass operation timings ce avd oe a16:a23 v pp we a/dq0: a/dq15 1us t vps v il or v ih v id t vpp pa pa don?t care a0h pd don?t care ce avd oe a16:a23 v pp we a/dq0: a/dq15 1us t vps v il or v ih v id t vpp ba ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase unlock bypass program operations(accelerated program) unlock bypass block erase operations notes: 1. v pp can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operations. 3. conventional program/erase commands as well as unlo ck bypass program/erase commands can be used when the v id is applied to vpp.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 38 switching waveforms notes: 1. va = valid address. when the internal routine operation is complete, and data polling will output true data. figure 15. data polling timings (during internal routine) notes: 1. va = valid address. when the internal routine operation is complete, the toggle bits will stop toggling. figure 16. toggle bit timings(duri ng internal routine) data polling operations toggle bit operations t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe a/dq0: a/dq15 rdy va va a16-a23 t rdys status data va va status data t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe a/dq0: a/dq15 rdy va va a16-a23 t rdys status data va va status data
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 39 switching waveforms t wc ce oe we a/dq0: avd a/dq15 a16-a23 note: breakpoints in waveforms indicate that system may alternatel y read array data from the ?non-busy bank? and checking the status of the program or erase operation in the ?busy? bank. figure 17. read while write operation pa/ba pd/30h ra ra 555h aah pa/ba ra ra rd rd last cycle in program or block erase command sequence read status in same bank and/or array data from other bank t rc t rc t wc t oe t oeh t wph t wp t aa t oeh t ds t dh t sr/w t as t ah t ghwl command sequences read while write operations program or erase begin another
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 40 crossing of first word boundary in burst read mode the additional clock insertion for word boundary is needed only at the first crossing of word boundary. this means that no addt ional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. also, the number of addtional clock cycle for the first word boundary can vary from zero to fourteen cycles, and the exact number of additional clock cycle depends on th e start- ing address of burst read and programmable wait state settings. for example, if the starting address is 16n +15 (the worst case) and programmable wait state setting(a<14:11>) is "0011" (which means data is valid on the 7th active clk edge after avd transition to vih), six addi tional clock cycle is needed. similarly, if the starting address is 16n+15 (the worst case) and programmable wait state setting(a<14:11>) is "0010" (which me ans data is valid on the 6th active clk edge after avd transition to vih), five additional clock cycle is needed. below table shows the starting address vs. addtional clock cycles for first word boundary. starting address vs. additional cl ock cycles for fi rst word boundary srarting address group for burst read the residue of (address/16) lsb bits of address additional clock cycles for first word boundary (note1) a<14:11> "0000" valid data : 4th clk a<14:11> "0001" valid data : 5th clk a<14:11> "0010" valid data : 6th clk ... a<14:11> "1011" valid data : 15th clk 16n 0 0000 0 cycle 0 cycl e 0 cycle ... 0 cycle 16n+1 1 0001 0 cycle 0 cycl e 0 cycle ... 0 cycle 16n+2 2 0010 0 cycle 0 cycl e 0 cycle ... 1 cycle 16n+3 3 0011 0 cycle 0 cycle 0 cycle ... 2 cycle 16n+4 4 0100 0 cycle 0 cycl e 0 cycle ... 3 cycle 16n+5 5 0101 0 cycle 0 cycl e 0 cycle ... 4 cycle 16n+6 6 0110 0 cycle 0 cycle 0 cycle ... 5 cycle 16n+7 7 0111 0 cycle 0 cycle 0 cycle ... 6 cycle 16n+8 8 1000 0 cycle 0 cycl e 0 cycle ... 7 cycle 16n+9 9 1001 0 cycle 0 cycl e 0 cycle ... 8 cycle 16n+10 10 1010 0 cycle 0 c ycle 0 cycle ... 9 cycle 16n+11 11 1011 0 cycle 0 cycle 1 cycle ... 10 cycle 16n+12 12 1100 0 cycle 1 cycle 2 cycle ... 11 cycle 16n+13 13 1101 1 cycle 2 cycle 3 cycle ... 12 cycle 16n+14 14 1110 2 cycle 3 cycle 4 cycle ... 13 cycle 16n+15 15 1111 3 cycle 4 cycle 5 cycle ... 14 cycle note 1) address bit a<14:11> means the programmable wait state on burst mode configuration register. refer to table 7.
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 41 notes: 1. address boundry occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles are needed except for 1st boundary crossing. figure 18. crossing of first word boundary in burst read mode. case 1 : start from "16n" address group ce oe rdy clk address/ data bus avd t cez t oez t oer valid address 3d 41 42 43 40 30 3d 41 42 43 44 no additional cycle for first word boundary 3e 3c 3e 3f 3f 40 3c notes: 1. address boundry occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles ar e needed except for 1st boundary crossing. figure 19. crossing of first word boundary in burst read mode. case 2 : start from "16n+2" address group ce oe rdy clk address/ data bus avd t cez t oez t oer valid address 3d 41 42 43 40 32 3d 41 42 43 44 no additional cycle for first word boundary 3e 3c 3e 3f 3f 40 3c 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 7.5ns typ(133mhz). 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 7.5ns typ(133mhz).
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 42 notes: 1. address boundry occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles ar e needed except for 1st boundary crossing. figure 20. crossing of first word boundary in burst read mode. case 4 : start from "16n+4" address group ce oe clk address/ data bus avd t cez t oez t oer valid address 3f 41 42 43 40 33 3e 41 42 43 44 additional 1 cycle for first word boundary 3e 3d 3f 40 case3 : start from "16n+3" address group ce oe clk address/ data bus avd t cez t oez t oer valid address 3f 414243 40 34 3f 41 42 43 44 additional 2 cycle for first word boundary 40 3e 3d 3e rdy rdy 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 7.5ns typ(133mhz). 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 7.5ns typ(133mhz).
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 43 notes: 1. address boundry occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2. address 000000h is also a boundry crossing. 3. no additional clock cycles ar e needed except for 1st boundary crossing. figure 21. crossing of first word boundary in burst read mode. case5 : start from "16n+15" address group ce oe rdy clk address/ data bus avd t oer valid address 3f 40 3f 40 41 additional 13cycle for first word boundary 14 cycles for initial access shown. cr setting : a14=1, a13=0, a12=1, a11=0 3f 41 7.5ns typ(133mhz).
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 44 88-ball fbga package dimension and pin configuration < bottom view *1 > 521 63 4 87 f e d c b a e d d 1 e z a a1 *2: top view *1: bottom view b se sd m l k j h g e 1 a1 index mark e
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 45 symbol min typ max a- -1.20 a 1 0.25 - - e 7.90 8.00 8.10 e 1 -5.60- d 10.90 11.0 11.10 d 1 -8.80- e - 0.80 - b 0.40 0.45 0.50 z--0.10 se - 0.40 - sd - 0.40 - [unit:mm] #a1 ball origin indicator k8f5615etm sec week xxxx es 88-ball (8x11) fbga 123456 78 adu du du du bnc nc wp vss vcc vcc nc nc c a20 rfu nc vss rfu clk dpd nc d nc a23 rfu nc rfu nc nc nc e a21 nc nc nc avd vpp a17 a22 f a16 nc rfu reset we a19 nc a18 g nc a/dq7 a/dq13 a/dq5 a/dq10 a/dq2 rdy nc h rfu a/dq15 a/dq14 a/dq12 a/dq3 a/dq1 a/dq8 nc jrfu oe a/dq6 a/dq4 a/dq11 a/dq9 a/dq0 vccq kce rfu rfu rfu vccq vcc vccq rfu l vss vss vccq vcc vss vss vss vss mdu du du du < top view *2 > pin description pin name pin function a16 - a23 address inputs a/dq0 - a/dq15 multiplexed address/data input/output ce chip enable oe output enable reset hardware reset v pp accelerates programming we write enable wp hardware write protection input clk clock rdy ready output avd address valid input dpd deep power down vcc power supply v ss ground
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 46 44-ball fbga package dimension and pin configuration < bottom view *1 > 521 63 4 8 97 d c b a e d d 1 e z a a1 *2: top view *1: bottom view b 10 1.00 se sd 1.00 a1 index mark e e 1
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 47 symbol min typ max a- -1.00 a 1 0.15 - - e 7.90 8.00 8.10 e 1 -4.50- d 8.90 9.00 9.10 d 1 -1.50- e - 0.50 - b 0.25 0.30 0.35 z--0.08 se - 0.25 - sd - 0.25 - [unit:mm] #a1 ball origin indicator k8f5615etm sec week xxxx es 44-ball (8x9) fbga 123456 78910 a rdy a21 vss clk vcc we vpp a19 a17 a22 bvcc a16 a20avd a23 reset wp a18 ce vss c vss a/dq7 a/dq6 a/dq13 a/dq12 a/dq3 a/dq2 a/dq9 a/dq8 oe d a/dq15 a/dq14 vss a/dq5 a/dq4 a/dq11 a/dq10 vcc a/dq1 a/dq0 < top view *2 > pin description pin name pin function a16 - a23 address inputs a/dq0 - a/dq15 multiplexed address/data input/output ce chip enable oe output enable reset hardware reset v pp accelerates programming we write enable wp hardware write protection input clk clock rdy ready output avd address valid input vcc power supply v ss ground
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 48 table 12-1. top boot block address table bank block block size (x16) address range bank 0 ba258 16 kwords ffc000h-ffffffh ba257 16 kwords ff8000h-ffbfffh ba256 16 kwords ff4000h-ff7fffh ba255 16 kwords ff0000h-ff3fffh ba254 64 kwords fe0000h-feffffh ba253 64 kwords fd0000h-fdffffh ba252 64 kwords fc0000h-fcffffh ba251 64 kwords fb0000h-fbffffh ba250 64 kwords fa0000h-faffffh ba249 64 kwords f90000h-f9ffffh ba248 64 kwords f80000h-f8ffffh ba247 64 kwords f70000h-f7ffffh ba246 64 kwords f60000h-f6ffffh ba245 64 kwords f50000h-f5ffffh ba244 64 kwords f40000h-f4ffffh ba243 64 kwords f30000h-f3ffffh ba242 64 kwords f20000h-f2ffffh ba241 64 kwords f10000h-f1ffffh ba240 64 kwords f00000h-f0ffffh bank 1 ba239 64 kwords ef0000h-efffffh ba238 64 kwords ee0000h-eeffffh ba237 64 kwords ed0000h-edffffh ba236 64 kwords ec0000h-ecffffh ba235 64 kwords eb0000h-ebffffh ba234 64 kwords ea0000h-eaffffh ba233 64 kwords e90000h-e9ffffh ba232 64 kwords e80000h-e8ffffh ba231 64 kwords e70000h-e7ffffh ba230 64 kwords e60000h-e6ffffh ba229 64 kwords e50000h-e5ffffh ba228 64 kwords e40000h-e4ffffh ba227 64 kwords e30000h-e3ffffh ba226 64 kwords e20000h-e2ffffh ba225 64 kwords e10000h-e1ffffh ba224 64 kwords e00000h-e0ffffh bank 2 ba223 64 kwords df0000h-dfffffh ba222 64 kwords de0000h-deffffh ba221 64 kwords dd0000h-ddffffh ba220 64 kwords dc0000h-dcffffh ba219 64 kwords db0000h-dbffffh ba218 64 kwords da0000h-daffffh ba217 64 kwords d90000h-d9ffffh ba216 64 kwords d80000h-d8ffffh ba215 64 kwords d70000h-d7ffffh ba214 64 kwords d60000h-d6ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 49 table 12-1. top boot block address table bank block block size (x16) address range bank 2 ba213 64 kwords d50000h-d5ffffh ba212 64 kwords d40000h-d4ffffh ba211 64 kwords d30000h-d3ffffh ba210 64 kwords d20000h-d2ffffh ba209 64 kwords d10000h-d1ffffh ba208 64 kwords d00000h-d0ffffh bank 3 ba207 64 kwords cf0000h-cfffffh ba206 64 kwords ce0000h-ceffffh ba205 64 kwords cd0000h-cdffffh ba204 64 kwords cc0000h-ccffffh ba203 64 kwords cb0000h-cbffffh ba202 64 kwords ca0000h-caffffh ba201 64 kwords c90000h-c9ffffh ba200 64 kwords c80000h-c8ffffh ba199 64 kwords c70000h-c7ffffh ba198 64 kwords c60000h-c6ffffh ba197 64 kwords c50000h-c5ffffh ba196 64 kwords c40000h-c4ffffh ba195 64 kwords c30000h-c3ffffh ba194 64 kwords c20000h-c2ffffh ba193 64 kwords c10000h-c1ffffh ba192 64 kwords c00000h-c0ffffh bank 4 ba191 64 kwords bf0000h-bfffffh ba190 64 kwords be0000h-beffffh ba189 64 kwords bd0000h-bdffffh ba188 64 kwords bc0000h-bcffffh ba187 64 kwords bb0000h-bbffffh ba186 64 kwords ba0000h-baffffh ba185 64 kwords b90000h-b9ffffh ba184 64 kwords b80000h-b8ffffh ba183 64 kwords b70000h-b7ffffh ba182 64 kwords b60000h-b6ffffh ba181 64 kwords b50000h-b5ffffh ba180 64 kwords b40000h-b4ffffh ba179 64 kwords b30000h-b3ffffh ba178 64 kwords b20000h-b2ffffh ba177 64 kwords b10000h-b1ffffh ba176 64 kwords b00000h-b0ffffh bank 5 ba175 64 kwords af0000h-afffffh ba174 64 kwords ae0000h-aeffffh ba173 64 kwords ad0000h-adffffh ba172 64 kwords ac0000h-acffffh ba171 64 kwords ab0000h-abffffh ba170 64 kwords aa0000h-aaffffh ba169 64 kwords a90000h-a9ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 50 table 12-1. top boot block address table bank block block size (x16) address range bank 5 ba168 64 kwords a80000h-a8ffffh ba167 64 kwords a70000h-a7ffffh ba166 64 kwords a60000h-a6ffffh ba165 64 kwords a50000h-a5ffffh ba164 64 kwords a40000h-a4ffffh ba163 64 kwords a30000h-a3ffffh ba162 64 kwords a20000h-a2ffffh ba161 64 kwords a10000h-a1ffffh ba160 64 kwords a00000h-a0ffffh bank 6 ba159 64 kwords 9f0000h-9fffffh ba158 64 kwords 9e0000h-9effffh ba157 64 kwords 9d0000h-9dffffh ba156 64 kwords 9c0000h-9cffffh ba155 64 kwords 9b0000h-9bffffh ba154 64 kwords 9a0000h-9affffh ba153 64 kwords 990000h-99ffffh ba152 64 kwords 980000h-98ffffh ba151 64 kwords 970000h-97ffffh ba150 64 kwords 960000h-96ffffh ba149 64 kwords 950000h-95ffffh ba148 64 kwords 940000h-94ffffh ba147 64 kwords 930000h-93ffffh ba146 64 kwords 920000h-92ffffh ba145 64 kwords 910000h-91ffffh ba144 64 kwords 900000h-90ffffh bank 7 ba143 64 kwords 8f0000h-8fffffh ba142 64 kwords 8e0000h-8effffh ba141 64 kwords 8d0000h-8dffffh ba140 64 kwords 8c0000h-8cffffh ba139 64 kwords 8b0000h-8bffffh ba138 64 kwords 8a0000h-8affffh ba137 64 kwords 890000h-89ffffh ba136 64 kwords 880000h-88ffffh ba135 64 kwords 870000h-87ffffh ba134 64 kwords 860000h-86ffffh ba133 64 kwords 850000h-85ffffh ba132 64 kwords 840000h-84ffffh ba131 64 kwords 830000h-83ffffh ba130 64 kwords 820000h-82ffffh ba129 64 kwords 810000h-81ffffh ba128 64 kwords 800000h-80ffffh bank 8 ba127 64 kwords 7f0000h-7fffffh ba126 64 kwords 7e0000h-7effffh ba125 64 kwords 7d0000h-7dffffh ba124 64 kwords 7c0000h-7cffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 51 table 12-1. top boot block address table bank block block size (x16) address range bank 8 ba123 64 kwords 7b0000h-7bffffh ba122 64 kwords 7a0000h-7affffh ba121 64 kwords 790000h-79ffffh ba120 64 kwords 780000h-78ffffh ba119 64 kwords 770000h-77ffffh ba118 64 kwords 760000h-76ffffh ba117 64 kwords 750000h-75ffffh ba116 64 kwords 740000h-74ffffh ba115 64 kwords 730000h-73ffffh ba114 64 kwords 720000h-72ffffh ba113 64 kwords 710000h-71ffffh ba112 64 kwords 700000h-70ffffh bank 9 ba111 64 kwords 6f0000h-6fffffh ba110 64 kwords 6e0000h-6effffh ba109 64 kwords 6d0000h-6dffffh ba108 64 kwords 6c0000h-6cffffh ba107 64 kwords 6b0000h-6bffffh ba106 64 kwords 6a0000h-6affffh ba105 64 kwords 690000h-69ffffh ba104 64 kwords 680000h-68ffffh ba103 64 kwords 670000h-67ffffh ba102 64 kwords 660000h-66ffffh ba101 64 kwords 650000h-65ffffh ba100 64 kwords 640000h-64ffffh ba99 64 kwords 630000h-63ffffh ba98 64 kwords 620000h-62ffffh ba97 64 kwords 610000h-61ffffh ba96 64 kwords 600000h-60ffffh bank 10 ba95 64 kwords 5f0000h-5fffffh ba94 64 kwords 5e0000h-5effffh ba93 64 kwords 5d0000h-5dffffh ba92 64 kwords 5c0000h-5cffffh ba91 64 kwords 5b0000h-5bffffh ba90 64 kwords 5a0000h-5affffh ba89 64 kwords 590000h-59ffffh ba88 64 kwords 580000h-58ffffh ba87 64 kwords 570000h-57ffffh ba86 64 kwords 560000h-56ffffh ba85 64 kwords 550000h-55ffffh ba84 64 kwords 540000h-54ffffh ba83 64 kwords 530000h-53ffffh ba82 64 kwords 520000h-52ffffh ba81 64 kwords 510000h-51ffffh ba80 64 kwords 500000h-50ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 52 table 12-1. top boot block address table bank block block size (x16) address range bank 11 ba79 64 kwords 4f0000h-4fffffh ba78 64 kwords 4e0000h-4effffh ba77 64 kwords 4d0000h-4dffffh ba76 64 kwords 4c0000h-4cffffh ba75 64 kwords 4b0000h-4bffffh ba74 64 kwords 4a0000h-4affffh ba73 64 kwords 490000h-49ffffh ba72 64 kwords 480000h-48ffffh ba71 64 kwords 470000h-47ffffh ba70 64 kwords 460000h-46ffffh ba69 64 kwords 450000h-45ffffh ba68 64 kwords 440000h-44ffffh ba67 64 kwords 430000h-43ffffh ba66 64 kwords 420000h-42ffffh ba65 64 kwords 410000h-41ffffh ba64 64 kwords 400000h-40ffffh bank 12 ba63 64 kwords 3f0000h-3fffffh ba62 64 kwords 3e0000h-3effffh ba61 64 kwords 3d0000h-3dffffh ba60 64 kwords 3c0000h-3cffffh ba59 64 kwords 3b0000h-3bffffh ba58 64 kwords 3a0000h-3affffh ba57 64 kwords 390000h-39ffffh ba56 64 kwords 380000h-38ffffh ba55 64 kwords 370000h-37ffffh ba54 64 kwords 360000h-36ffffh ba53 64 kwords 350000h-35ffffh ba52 64 kwords 340000h-34ffffh ba51 64 kwords 330000h-33ffffh ba50 64 kwords 320000h-32ffffh ba49 64 kwords 310000h-31ffffh ba48 64 kwords 300000h-30ffffh bank 13 ba47 64 kwords 2f0000h-2fffffh ba46 64 kwords 2e0000h-2effffh ba45 64 kwords 2d0000h-2dffffh ba44 64 kwords 2c0000h-2cffffh ba43 64 kwords 2b0000h-2bffffh ba42 64 kwords 2a0000h-2affffh ba41 64 kwords 290000h-29ffffh ba40 64 kwords 280000h-28ffffh ba39 64 kwords 270000h-27ffffh ba38 64 kwords 260000h-26ffffh ba37 64 kwords 250000h-25ffffh ba36 64 kwords 240000h-24ffffh ba35 64 kwords 230000h-23ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 53 table 12-1. top boot block address table bank block block size (x16) address range bank 13 ba34 64 kwords 220000h-22ffffh ba33 64 kwords 210000h-21ffffh ba32 64 kwords 200000h-20ffffh bank 14 ba31 64 kwords 1f0000h-1fffffh ba30 64 kwords 1e0000h-1effffh ba29 64 kwords 1d0000h-1dffffh ba28 64 kwords 1c0000h-1cffffh ba27 64 kwords 1b0000h-1bffffh ba26 64 kwords 1a0000h-1affffh ba25 64 kwords 190000h-19ffffh ba24 64 kwords 180000h-18ffffh ba23 64 kwords 170000h-17ffffh ba22 64 kwords 160000h-16ffffh ba21 64 kwords 150000h-15ffffh ba20 64 kwords 140000h-14ffffh ba19 64 kwords 130000h-13ffffh ba18 64 kwords 120000h-12ffffh ba17 64 kwords 110000h-11ffffh ba16 64 kwords 100000h-10ffffh bank 15 ba15 64 kwords 0f0000h-0fffffh ba14 64 kwords 0e0000h-0effffh ba13 64 kwords 0d0000h-0dffffh ba12 64 kwords 0c0000h-0cffffh ba11 64 kwords 0b0000h-0bffffh ba10 64 kwords 0a0000h-0affffh ba9 64 kwords 090000h-09ffffh ba8 64 kwords 080000h-08ffffh ba7 64 kwords 070000h-07ffffh ba6 64 kwords 060000h-06ffffh ba5 64 kwords 050000h-05ffffh ba4 64 kwords 040000h-04ffffh ba3 64 kwords 030000h-03ffffh ba2 64 kwords 020000h-02ffffh ba1 64 kwords 010000h-01ffffh ba0 64 kwords 000000h-00ffffh after entering otp block, any issued addresses should be in the range of otp block address. otp block address a23 ~ a8 block size (x16) address range* ffffh 512words fffe00h-ffffffh table 12-1-1. otp block addresses
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 54 table 12-2. bottom boot block address table bank block block size (x16) address range bank 15 ba258 64 kwords ff0000h-ffffffh ba257 64 kwords fe0000h-feffffh ba256 64 kwords fd0000h-fdffffh ba255 64 kwords fc0000h-fcffffh ba254 64 kwords fb0000h-fbffffh ba253 64 kwords fa0000h-faffffh ba252 64 kwords f90000h-f9ffffh ba251 64 kwords f80000h-f8ffffh ba250 64 kwords f70000h-f7ffffh ba249 64 kwords f60000h-f6ffffh ba248 64 kwords f50000h-f5ffffh ba247 64 kwords f40000h-f4ffffh ba246 64 kwords f30000h-f3ffffh ba245 64 kwords f20000h-f2ffffh ba244 64 kwords f10000h-f1ffffh ba243 64 kwords f00000h-f0ffffh bank 14 ba242 64 kwords ef0000h-efffffh ba241 64 kwords ee0000h-eeffffh ba240 64 kwords ed0000h-edffffh ba239 64 kwords ec0000h-ecffffh ba238 64 kwords eb0000h-ebffffh ba237 64 kwords ea0000h-eaffffh ba236 64 kwords e90000h-e9ffffh ba235 64 kwords e80000h-e8ffffh ba234 64 kwords e70000h-e7ffffh ba233 64 kwords e60000h-e6ffffh ba232 64 kwords e50000h-e5ffffh ba231 64 kwords e40000h-e4ffffh ba230 64 kwords e30000h-e3ffffh ba229 64 kwords e20000h-e2ffffh ba228 64 kwords e10000h-e1ffffh ba227 64 kwords e00000h-e0ffffh bank 13 ba226 64 kwords df0000h-dfffffh ba225 64 kwords de0000h-deffffh ba224 64 kwords dd0000h-ddffffh ba223 64 kwords dc0000h-dcffffh ba222 64 kwords db0000h-dbffffh ba221 64 kwords da0000h-daffffh ba220 64 kwords d90000h-d9ffffh ba219 64 kwords d80000h-d8ffffh ba218 64 kwords d70000h-d7ffffh ba217 64 kwords d60000h-d6ffffh ba216 64 kwords d50000h-d5ffffh ba215 64 kwords d40000h-d4ffffh ba214 64 kwords d30000h-d3ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 55 table 12-2. bottom boot block address table bank block block size (x16) address range bank 13 ba213 64 kwords d20000h-d2ffffh ba212 64 kwords d10000h-d1ffffh ba211 64 kwords d00000h-d0ffffh bank 12 ba210 64 kwords cf0000h-cfffffh ba209 64 kwords ce0000h-ceffffh ba208 64 kwords cd0000h-cdffffh ba207 64 kwords cc0000h-ccffffh ba206 64 kwords cb0000h-cbffffh ba205 64 kwords ca0000h-caffffh ba204 64 kwords c90000h-c9ffffh ba203 64 kwords c80000h-c8ffffh ba202 64 kwords c70000h-c7ffffh ba201 64 kwords c60000h-c6ffffh ba200 64 kwords c50000h-c5ffffh ba199 64 kwords c40000h-c4ffffh ba198 64 kwords c30000h-c3ffffh ba197 64 kwords c20000h-c2ffffh ba196 64 kwords c10000h-c1ffffh ba195 64 kwords c00000h-c0ffffh bank 11 ba194 64 kwords bf0000h-bfffffh ba193 64 kwords be0000h-beffffh ba192 64 kwords bd0000h-bdffffh ba191 64 kwords bc0000h-bcffffh ba190 64 kwords bb0000h-bbffffh ba189 64 kwords ba0000h-baffffh ba188 64 kwords b90000h-b9ffffh ba187 64 kwords b80000h-b8ffffh ba186 64 kwords b70000h-b7ffffh ba185 64 kwords b60000h-b6ffffh ba184 64 kwords b50000h-b5ffffh ba183 64 kwords b40000h-b4ffffh ba182 64 kwords b30000h-b3ffffh ba181 64 kwords b20000h-b2ffffh ba180 64 kwords b10000h-b1ffffh ba179 64 kwords b00000h-b0ffffh bank 10 ba178 64 kwords af0000h-afffffh ba177 64 kwords ae0000h-aeffffh ba176 64 kwords ad0000h-adffffh ba175 64 kwords ac0000h-acffffh ba174 64 kwords ab0000h-abffffh ba173 64 kwords aa0000h-aaffffh ba172 64 kwords a90000h-a9ffffh ba171 64 kwords a80000h-a8ffffh ba170 64 kwords a70000h-a7ffffh ba169 64 kwords a60000h-a6ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 56 table 12-2. bottom boot block address table bank block block size (x16) address range bank 10 ba168 64 kwords a50000h-a5ffffh ba167 64 kwords a40000h-a4ffffh ba166 64 kwords a30000h-a3ffffh ba165 64 kwords a20000h-a2ffffh ba164 64 kwords a10000h-a1ffffh ba163 64 kwords a00000h-a0ffffh bank 9 ba162 64 kwords 9f0000h-9fffffh ba161 64 kwords 9e0000h-9effffh ba160 64 kwords 9d0000h-9dffffh ba159 64 kwords 9c0000h-9cffffh ba158 64 kwords 9b0000h-9bffffh ba157 64 kwords 9a0000h-9affffh ba156 64 kwords 990000h-99ffffh ba155 64 kwords 980000h-98ffffh ba154 64 kwords 970000h-97ffffh ba153 64 kwords 960000h-96ffffh ba152 64 kwords 950000h-95ffffh ba151 64 kwords 940000h-94ffffh ba150 64 kwords 930000h-93ffffh ba149 64 kwords 920000h-92ffffh ba148 64 kwords 910000h-91ffffh ba147 64 kwords 900000h-90ffffh bank 8 ba146 64 kwords 8f0000h-8fffffh ba145 64 kwords 8e0000h-8effffh ba144 64 kwords 8d0000h-8dffffh ba143 64 kwords 8c0000h-8cffffh ba142 64 kwords 8b0000h-8bffffh ba141 64 kwords 8a0000h-8affffh ba140 64 kwords 890000h-89ffffh ba139 64 kwords 880000h-88ffffh ba138 64 kwords 870000h-87ffffh ba137 64 kwords 860000h-86ffffh ba136 64 kwords 850000h-85ffffh ba135 64 kwords 840000h-84ffffh ba134 64 kwords 830000h-83ffffh ba133 64 kwords 820000h-82ffffh ba132 64 kwords 810000h-81ffffh ba131 64 kwords 800000h-80ffffh bank 7 ba130 64 kwords 7f0000h-7fffffh ba129 64 kwords 7e0000h-7effffh ba128 64 kwords 7d0000h-7dffffh ba127 64 kwords 7c0000h-7cffffh ba126 64 kwords 7b0000h-7bffffh ba125 64 kwords 7a0000h-7affffh ba124 64 kwords 790000h-79ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 57 table 12-2. bottom boot block address table bank block block size (x16) address range bank 7 ba123 64 kwords 780000h-78ffffh ba122 64 kwords 770000h-77ffffh ba121 64 kwords 760000h-76ffffh ba120 64 kwords 750000h-75ffffh ba119 64 kwords 740000h-74ffffh ba118 64 kwords 730000h-73ffffh ba117 64 kwords 720000h-72ffffh ba116 64 kwords 710000h-71ffffh ba115 64 kwords 700000h-70ffffh bank 6 ba114 64 kwords 6f0000h-6fffffh ba113 64 kwords 6e0000h-6effffh ba112 64 kwords 6d0000h-6dffffh ba111 64 kwords 6c0000h-6cffffh ba110 64 kwords 6b0000h-6bffffh ba109 64 kwords 6a0000h-6affffh ba108 64 kwords 690000h-69ffffh ba107 64 kwords 680000h-68ffffh ba106 64 kwords 670000h-67ffffh ba105 64 kwords 660000h-66ffffh ba104 64 kwords 650000h-65ffffh ba103 64 kwords 640000h-64ffffh ba102 64 kwords 630000h-63ffffh ba101 64 kwords 620000h-62ffffh ba100 64 kwords 610000h-61ffffh ba99 64 kwords 600000h-60ffffh bank 5 ba98 64 kwords 5f0000h-5fffffh ba97 64 kwords 5e0000h-5effffh ba96 64 kwords 5d0000h-5dffffh ba95 64 kwords 5c0000h-5cffffh ba94 64 kwords 5b0000h-5bffffh ba93 64 kwords 5a0000h-5affffh ba92 64 kwords 590000h-59ffffh ba91 64 kwords 580000h-58ffffh ba90 64 kwords 570000h-57ffffh ba89 64 kwords 560000h-56ffffh ba88 64 kwords 550000h-55ffffh ba87 64 kwords 540000h-54ffffh ba86 64 kwords 530000h-53ffffh ba85 64 kwords 520000h-52ffffh ba84 64 kwords 510000h-51ffffh ba83 64 kwords 500000h-50ffffh bank 4 ba82 64 kwords 4f0000h-4fffffh ba81 64 kwords 4e0000h-4effffh ba80 64 kwords 4d0000h-4dffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 58 table 12-2. bottom boot block address table bank block block size (x16) address range bank 4 ba79 64 kwords 4c0000h-4cffffh ba78 64 kwords 4b0000h-4bffffh ba77 64 kwords 4a0000h-4affffh ba76 64 kwords 490000h-49ffffh ba75 64 kwords 480000h-48ffffh ba74 64 kwords 470000h-47ffffh ba73 64 kwords 460000h-46ffffh ba72 64 kwords 450000h-45ffffh ba71 64 kwords 440000h-44ffffh ba70 64 kwords 430000h-43ffffh ba69 64 kwords 420000h-42ffffh ba68 64 kwords 410000h-41ffffh ba67 64 kwords 400000h-40ffffh bank 3 ba66 64 kwords 3f0000h-3fffffh ba65 64 kwords 3e0000h-3effffh ba64 64 kwords 3d0000h-3dffffh ba63 64 kwords 3c0000h-3cffffh ba62 64 kwords 3b0000h-3bffffh ba61 64 kwords 3a0000h-3affffh ba60 64 kwords 390000h-39ffffh ba59 64 kwords 380000h-38ffffh ba58 64 kwords 370000h-37ffffh ba57 64 kwords 360000h-36ffffh ba56 64 kwords 350000h-35ffffh ba55 64 kwords 340000h-34ffffh ba54 64 kwords 330000h-33ffffh ba53 64 kwords 320000h-32ffffh ba52 64 kwords 310000h-31ffffh ba51 64 kwords 300000h-30ffffh bank 2 ba50 64 kwords 2f0000h-2fffffh ba49 64 kwords 2e0000h-2effffh ba48 64 kwords 2d0000h-2dffffh ba47 64 kwords 2c0000h-2cffffh ba46 64 kwords 2b0000h-2bffffh ba45 64 kwords 2a0000h-2affffh ba44 64 kwords 290000h-29ffffh ba43 64 kwords 280000h-28ffffh ba42 64 kwords 270000h-27ffffh ba41 64 kwords 260000h-26ffffh ba40 64 kwords 250000h-25ffffh ba39 64 kwords 240000h-24ffffh ba38 64 kwords 230000h-23ffffh ba37 64 kwords 220000h-22ffffh ba36 64 kwords 210000h-21ffffh ba35 64 kwords 200000h-20ffffh
nor flash memory k8f56(57)15et(b)m revision 1.2 september, 2006 59 table 12-2. bottom boot block address table bank block block size (x16) address range bank 1 ba34 64 kwords 1f0000h-1fffffh ba33 64 kwords 1e0000h-1effffh ba32 64 kwords 1d0000h-1dffffh ba31 64 kwords 1c0000h-1cffffh ba30 64 kwords 1b0000h-1bffffh ba29 64 kwords 1a0000h-1affffh ba28 64 kwords 190000h-19ffffh ba27 64 kwords 180000h-18ffffh ba26 64 kwords 170000h-17ffffh ba25 64 kwords 160000h-16ffffh ba24 64 kwords 150000h-15ffffh ba23 64 kwords 140000h-14ffffh ba22 64 kwords 130000h-13ffffh ba21 64 kwords 120000h-12ffffh ba20 64 kwords 110000h-11ffffh ba19 64 kwords 100000h-10ffffh bank 0 ba18 64 kwords 0f0000h-0fffffh ba17 64 kwords 0e0000h-0effffh ba16 64 kwords 0d0000h-0dffffh ba15 64 kwords 0c0000h-0cffffh ba14 64 kwords 0b0000h-0bffffh ba13 64 kwords 0a0000h-0affffh ba12 64 kwords 090000h-09ffffh ba11 64 kwords 080000h-08ffffh ba10 64 kwords 070000h-07ffffh ba9 64 kwords 060000h-06ffffh ba8 64 kwords 050000h-05ffffh ba7 64 kwords 040000h-04ffffh ba6 64 kwords 030000h-03ffffh ba5 64 kwords 020000h-02ffffh ba4 64 kwords 010000h-01ffffh ba3 16 kwords 00c000h-00ffffh ba2 16 kwords 008000h-00bfffh ba1 16 kwords 004000h-007fffh ba0 16 kwords 000000h-003fffh table 12-2-1. otp block addresses after entering otp block, any issued addresses should be in the range of otp block address. otp block address a23 ~ a8 block size (x16) address range* 0000h 512 words 000000h-0001ffh

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